Let´s explore the ladder logic equivalent of a D latch, modified from the basic ladder diagram of an S-R latch: An application for the D latch is a 1-bit memory circuit. Both of these latches has invalid states, which must be avoided if possible. The D latch is nothing more than a gated S-R latch with an inverter added to make R the complement (inverse) of S. The S-R latch can be divided into two types, NAND S-R Latch which has active LOW input, and NOR S-R Latch which has active HIGH input. In conclusion, although the S-R latch is considered the most basic type of sequential logic component, it is still a very important component because other more complex type of components are actually formed by combining the S-R latch with other types of components. This result is invalid because the output Q+ must be the inverse of the output. While the S and R inputs are both low, feedback maintains the Q and Q outputs in. The stored bit is present on the output marked Q. It can be constructed from a pair of cross-coupled NOR logic gates. When both the inputs of a S-R NOR latch are active HIGH which are 1, the output cannot be found (invalid) because both of the outputs Q+ and are 0. When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. As can be seen from Table 2, the operation of the SR-NOR Latch can be considered similar to the SR-NAND Latch but requires the use of opposite logic level. In experiment two, the same experiment is carried out, but the SR-NAND Latch is replaced with a SR-NOR Latch. Only when the enable input is activated (1) will the latch respond to the S and R inputs. Consequently, the circuit behaves as though S and R were both 0, latching the Q and not-Q outputs in their last states.
When both the inputs of a S-R NAND latch are active LOW which are 0, the output cannot be found (invalid) because both of the outputs Q+ and are 1. When the E0, the outputs of the two AND gates are forced to 0, regardless of the states of either S or R. This 0 output is then coupled back to the G2 gate, ensuring that the output remains 1 even when the input R changes state. When this happens, the output + becomes 1, this output is coupled back to the G1 gate*, since both the feedback input from the G2 gate* and the S input is 1, the output Q goes to 0.
The latch will remain in this state until a 0 input is applied to the R input. Level sensitive cross-coupled Nor gates active high inputs (only one can be active) cross-coupled Nand gates active low. From experiment 1, it can be seen that when both inputs of the SR-NAND Latch and, as well as the output is 1, the output sets the latch into the SET state. This discussion revolves around the explanation on how the inputs affect the values of and Q+. In the results section, the and Q are complements of each other and are the previous values of the output of the SR Latch whereas and Q+ are complements of each other and represents the present values of the output of the SR Latch.